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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999, 2000 mos integrated circuit m m m m pd16341 96-bit ac-pdp driver data sheet document no. s14076ej2v0ds00 (2nd edition) date published march 2000 ns cp (k) printed in japan the mark ? ? ? ? shows major revised points. description the m pd16341 is high withstand voltage cmos driver designed for flat display panels such as pdps, vfds and els. it consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage cmos driver. the logic block is designed to operate using a 5-v power supply interface enabling direct connection to a gate array or a microcontroller. in addition, the m pd16341 achieves low power dissipation by employing the cmos structure while having a high withstand voltage output (120 v, +15/ - 25 ma max.). features 2-/3-/4-/6-ch input port switching is possible using ibs1 and ibs2 pins data control with transfer clock (external) and latch high-speed data transfer (f max. = 40 mhz min. at data latch) (f max . = 25 mhz min. at cascade connection) high withstand output voltage: 120 v, +15/C25 ma max. 5-v cmos input interface high withstand voltage cmos structure ordering information part number package m pd16341 module remark consult an nec sales representative regarding the module. since the module characteristics is based on the module specifications, there may be differences between the contents written in this document and real characteristics. ? ? ?
data sheet s14076ej2v0ds00 2 m m m m pd16341 1. block diagram (1) (ibs1 = h, ibs2 = h, 2-bit input, 48-bit length shift register) hz /le /lblk s 95 s 96 /l 96 le v dd2 o 1 v ss2 v ss2 o 96 v dd2 /l 1 s 1 s 2 a 2 b 2 a 1 b 1 sr 1 note a 1 clk s 95 s 1 clk r,/l b 1 s 3 sr 2 note a 2 clk s 96 s 2 b 2 s 4 /hblk r,/l clr /clr r,/l clr note sr n : 48-bit shift register remark /xxx indicates active low si gnal.
data sheet s14076ej2v0ds00 3 m m m m pd16341 1. block diagram (2) (ibs1 = h, ibs2 = l, 3-bit input, 32-bit length shift register) hz /le /lblk s 94 s 95 s 96 /l 96 le v dd2 o 1 v ss2 v ss2 o 96 v dd2 /l 1 s 1 s 2 s 3 a 2 b 2 a 1 b 1 sr 1 note a 1 clk s 94 s 1 clk r,/l b 1 s 4 sr 2 note a 2 clk s 95 s 2 b 2 s 5 /hblk r,/l clr /clr r,/l clr a 3 b 3 sr 3 note a 3 clk s 96 s 3 b 3 s 6 r,/l clr note sr n : 32-bit shift register
data sheet s14076ej2v0ds00 4 m m m m pd16341 1. block diagram (3) (ibs1 = l, ibs2 = h, 4-bit input, 24-bit length shift register) hz /le /lblk s 93 s 94 s 95 s 96 /l 96 le v dd2 o 1 v ss2 v ss2 o 96 v dd2 /l 1 s 1 s 2 s 3 s 4 a 2 b 2 a 1 b 1 sr 1 note a 1 clk s 93 s 1 clk r,/l b 1 s 5 sr 2 note /hblk r,/l clr /clr a 3 b 3 sr 3 note a 3 s 95 s 3 s 7 a 2 clk s 94 s 2 r,/l b 2 s 6 clr clk r,/l b 3 clr a 4 b 4 sr 4 note a 4 s 96 s 4 s 8 clk r,/l b 4 clr note sr n : 24-bit shift register
data sheet s14076ej2v0ds00 5 m m m m pd16341 1. block diagram (4) (ibs1 = l, ibs2 = l, 6-bit input, 16-bit length shift register) hz /le /lblk s 91 s 92 s 93 s 94 s 95 s 96 /l 96 le v dd2 o 1 v ss2 v ss2 o 96 v dd2 /l 1 s 1 s 2 s 3 s 4 s 5 s 6 a 2 b 2 a 1 b 1 sr 1 note a 1 clk s 91 s 1 clk r,/l b 1 s 7 sr 2 note /hblk r,/l clr /clr a 3 b 3 sr 3 note a 3 s 93 s 3 s 9 a 2 clk s 92 s 2 r,/l b 2 s 8 clr clk r,/l b 3 clr a 4 b 4 sr 4 note a 4 s 94 s 4 s 10 clk r,/l b 4 clr a 5 b 5 sr 5 note a 5 s 95 s 5 s 11 clk r,/l b 5 clr a 6 b 6 sr 6 note a 6 s 96 s 6 s 12 clk r,/l b 6 clr note sr n : 16-bit shift register
data sheet s14076ej2v0ds00 6 m m m m pd16341 2. pin functions symbol pin name description /lblk low blanking input /lblk = l : all output = l /hblk high blanking input /hblk = l : all output = h /le latch enable input latch executed on fall hz output high impedance make all output high impedance by input h /clr register clear input inputting the low level of this signal clears the entire contents of the shift register to low level. a n right data input/output note when r,/l = h, a n : input b n : output b n left data input/output note when r,/l = l, a n : output b n : input clk clock input shift executed on rise r,/l shift control input right shift mode when r,/l = h (in the case of 3-ch input) sr 1 : a 1 ? s 1 .......s 94 ? b 1 (same direction for sr 2 and sr 3 ) left shift mode when r,/l = l (in the case of 3-ch input) sr 1 : b 1 ? s 94 .......s 1 ? a 1 (same direction for sr 2 and sr 3 ) the shift direction is the same in the case of 2-/4-/6-ch input. ibs1 ibs2 input mode h l 3-bit input, 32-bit length shift register l l 6-bit input, 16-bit length shift register h h 2-bit input, 48-bit length shift register ibs1,ibs2 input mode switch l h 4-bit input, 24-bit length shift register o 1 to o 96 high withstand voltage output 120 v v dd1 logic power supply 5 v 10 % v dd2 driver power supply 20 to 110 v v ss1 logic ground connect to system ground v ss2 driver ground connect to system ground note when input mode is 2-/3-/4-bit, set unused input and output pins l level. to use for module, the back side of ic chip must be held at the v ss (gnd) level.
data sheet s14076ej2v0ds00 7 m m m m pd16341 3. truth table shift register block input output r,/l clk a b shift register h - output note1 right shift execution hh or l input output hold l - output note2 left shift execution l h or l output input hold notes 1. the data of s 91 to s 93 (in the case of 3-ch input) is shifted to s 94 to s 96 at the rising of the clock and then output from b 1 to b 3 , respectively. this shift ? output operation is the same in the case of 2-/4-/6-ch input. 2. the data of s 4 to s 6 (in the case of 3-ch input) is shifted to s 1 to s 3 at the rising of the clock and then output from a 1 to a 3 , respectively. this shift ? output operation is the same in the case of 2-/4-/6-ch input. latch block /le output state of latch block (/l n ) latch s n data h or l hold latch (output) data driver block a (b) /hblk /lblk hz output state of driver block x l h l all driver output : h x x l l all driver output : l x x x h all driver output : high impedance lhhll hhhlh remark x : h or l, h : high level, l : low level
data sheet s14076ej2v0ds00 8 m m m m pd16341 4. timing chart (1) (ibs1 = h, ibs2 = h: 2-bit input, right shift) /clr /le high impedance high impedance high impedance high impedance clk a 1 (b 2 ) a 2 (b 1 ) s 1 (s 96 ) s 2 (s 95 ) s 3 (s 94 ) s 4 (s 93 ) o 1 (o 96 ) hz /lblk /hblk o 2 (o 95 ) o 3 (o 94 ) o 4 (o 93 ) latch at falling edge remark values in parentheses are when r,/l = l.
data sheet s14076ej2v0ds00 9 m m m m pd16341 4. timing chart (2) (ibs1 = h, ibs2 = l: 3-bit input, right shift) /clr /le high impedance high impedance high impedance clk a 1 (b 3 ) a 2 (b 2 ) s 1 (s 96 ) s 2 (s 95 ) s 3 (s 94 ) s 4 (s 93 ) o 1 (o 96 ) hz /lblk /hblk o 2 (o 95 ) o 3 (o 94 ) o 4 (o 93 ) latch at falling edge a 3 (b 1 ) high impedance high impedance high impedance s 5 (s 92 ) s 6 (s 91 ) o 5 (o 92 ) o 6 (o 91 ) remark values in parentheses are when r,/l = l.
data sheet s14076ej2v0ds00 10 m m m m pd16341 4. timing chart (3) (ibs1 = l, ibs2 = h: 4-bit input, right shift) /clr /le high impedance high impedance high impedance clk a 1 (b 4 ) a 2 (b 3 ) s 1 (s 96 ) s 2 (s 95 ) s 3 (s 94 ) s 4 (s 93 ) o 1 (o 96 ) hz /lblk /hblk o 2 (o 95 ) o 3 (o 94 ) o 4 (o 93 ) latch at falling edge a 3 (b 2 ) high impedance high impedance s 5 (s 92 ) s 6 (s 91 ) o 5 (o 92 ) o 6 (o 91 ) high impedance a 4 (b 1 ) remark values in parentheses are when r,/l = l.
data sheet s14076ej2v0ds00 11 m m m m pd16341 4. timing chart (4) (ibs1 = l, ibs2 = l: 6-bit input, right shift) /clr /le high impedance high impedance high impedance clk a 1 (b 6 ) a 2 (b 5 ) s 1 (s 96 ) s 2 (s 95 ) s 3 (s 94 ) s 4 (s 93 ) o 1 (o 96 ) hz /lblk /hblk o 2 (o 95 ) o 3 (o 94 ) o 4 (o 93 ) latch at falling edge a 3 (b 4 ) high impedance high impedance s 5 (s 92 ) s 7 (s 90 ) o 6 (o 91 ) o 7 (o 90 ) high impedance a 4 (b 3 ) a 6 (b 1 ) a 5 (b 2 ) s 6 (s 91 ) o 5 (o 92 ) high impedance remark values in parentheses are when r,/l = l.
data sheet s14076ej2v0ds00 12 m m m m pd16341 5. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = = = = v ss2 = = = = 0 v) parameter symbol conditions ratings unit logic supply voltage v dd1 C0.5 to +6.0 v driver supply voltage v dd2 C0.5 to +120 v logic input voltage v i C0.5 to v dd1 + 0.5 v driver output current i o2 +15 / C25 ma operating junction temperature t j +125 c storage temperature t stg C65 to +150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = - - - - 40 to +85 c, v ss1 = = = = v ss2 = = = = 0 v) parameter symbol conditions min. typ. max. unit logic supply voltage v dd1 4.5 5.0 5.5 v driver supply voltage v dd2 20 110 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.2 v dd1 v i oh2 C20 ma driver output current i ol2 13 ma electrical characteristics (t a = 25 c, v dd1 = = = = 5.0 v, v dd2 = = = = 110 v, v ss1 = = = = v ss2 = = = = 0 v) parameter symbol conditions min. typ. max. unit high-level output voltage v oh1 logic, i oh1 = C1.0 ma 0.9 v dd1 v dd1 v low-level output voltage v ol1 logic, i ol1 = 1.0 ma 0 0.1 v dd1 v v oh21 o 1 to o 96 i oh2 = C0.4 ma 109 v high-level output voltage v oh22 i oh2 = C4.3 ma 105 v v ol21 i ol2 = 1.6 ma 1.0 v low-level output voltage v ol22 i ol2 = 13 ma 10 v input leakage current i il v 1 = v dd1 or v ss1 1.0 m a high-level intput voltage v ih 0.7 v dd1 v low-level input voltage v il 0.2 v dd1 v static current dissipation i dd1 logic, t a = C40 to +85 c 500 m a logic, t a = 25 c 300 m a i dd2 driver, t a = C40 to +85 c 1000 m a driver, t a = 25 c 100 m a ? ? ? ?
data sheet s14076ej2v0ds00 13 m m m m pd16341 switching characteristics (t a = +25 c, v dd1 = = = = 5.0 v, v dd2 = = = = 110 v, v ss1 = = = = v ss2 = = = = 0 v, logic c l = = = = 15 pf, driver c l = = = = 50 pf, t r = = = = t f = = = = 6.0 ns) parameter symbol conditions min. typ. max. unit propagation delay time t phl1 clk - ? a/b 34 ns t plh1 34 ns t phl2 /le ? o 1 to o 96 180 ns t plh2 180 ns t phl3 /hblk ? o 1 to o 96 165 ns t plh3 165 ns t phl4 /lblk ? o 1 to o 96 160 ns t plh4 160 ns t phz hz ? o 1 to o 96 300 ns t pzh r l = 10 k w 180 ns t plz 300 ns t pzl 180 ns rise time t tlh o 1 to o 96 360 ns t tlz o 1 to o 96 3 m s t tzh r l = 10 k w 360 ns t thl o 1 to o 96 450 ns t thz o 1 to o 96 3 m s fall time t tzl r l = 10 k w 450 ns maximum clock frequency f max. when data is read, duty = 50 % 40 mhz cascade connection : duty = 50 % 25 mhz input capacitance c i 15 pf timing requirement (t a = C40 to +85 c, v dd1 = 4.5 to 5.5 v, v ss1 = = = = v ss2 = = = = 0 v, t r = t f = = = = 6.0 ns) parameter symbol conditions min. typ. max. unit clock pulse width pw clk(h) pw clk(l) 12 ns latch enable pulse width pw /le 12 ns blank pulse width pw /blk /hblk, /lblk 600 ns hz pulse width pw hz r l = 10 k w 3.3 m s /clr pulse width pw /clr 12 ns data setup time t setup 4ns data hold time t hold 6ns latch enable time t /le1 12 ns t /le2 12 ns /clr timing t /clr 6ns ? ? ?
data sheet s14076ej2v0ds00 14 m m m m pd16341 6. switching characteristics waveform (1/3) clk a n /b n (input) b n /a n (output) /le clk o n o n 1/f max. pw clk (h) pw clk (l) t setup t hold 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % 50 % t phl1 t plh1 v ss1 v ss1 v oh1 v ol1 v ss1 v ol2 v oh2 v ol2 v oh2 v ss1 50 % 50 % 90 % 10 % t plh2 t phl2 t /le2 t /le1 pw /le(h) v dd1 v dd1 10 % t thl 90 % t tlh v dd1 v dd1 pw /le(l)
data sheet s14076ej2v0ds00 15 m m m m pd16341 6. switching characteristics waveform (2/3) /lblk o n /hblk clk pw /blk t phl4 90 % 10 % 50 % 50 % v ss1 v ol2 v dd1 v ss1 v ol2 v ol2 v oh2 t /clr v dd1 v oh2 v oh2 v ss1 t plh4 pw /blk t plh3 10 % 50 % 50 % t phl3 90 % /clr pw /clr 50 % 50 % v dd1 50 % rising edge of clock when data is valid. o n
data sheet s14076ej2v0ds00 16 m m m m pd16341 6. switching characteristics waveform (3/3) o n o n hz v oh2 v ol2 v o (h) v dd1 90 % 10 % 10 % t pzh t thz t phz t tzh 90 % 10 % t plz t tlz t pzl t tzl 50 % pw hz 50 % 90 % 10 % 90 % v ss1 v o (l)
data sheet s14076ej2v0ds00 17 m m m m pd16341 [memo]
data sheet s14076ej2v0ds00 18 m m m m pd16341 [memo]
data sheet s14076ej2v0ds00 19 m m m m pd16341 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16341 reference documents nec semiconductor device reliability/quality control system(c10983e) quality grades to necs semiconductor devices(c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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